ISBN: 9780470516164

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, a… More...

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and;examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.; EPUB; Scientific, Technical and Medical > Electronics & communications engineering > Electronics engineeri, Wiley<

2008, ISBN: 9780470516164

Interest in latchup is being renewed with the evolution ofcomplimentary metal-oxide semiconductor (CMOS) technology,metal-oxide-semiconductor field-effect transistor (MOSFET) scaling,and … More...

Interest in latchup is being renewed with the evolution ofcomplimentary metal-oxide semiconductor (CMOS) technology,metal-oxide-semiconductor field-effect transistor (MOSFET) scaling,and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, withinsight into the physics, technology and circuit issues involved,are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology andtheir sensitivity to present day latchup phenomena, from basicover-voltage and over-current conditions, single event latchup(SEL) and cable discharge events (CDE), to latchup dominophenomena. It contains chapters focusing on bipolar physics,latchup theory, latchup and guard ring characterization structures,characterization testing, product level test systems, product leveltesting and experimental results. Discussions on state-of-the-artsemiconductor processes, design layout, and circuit level andsystem level latchup solutions are also included, as well as: * latchup semiconductor process solutions for both CMOS toBiCMOS, such as shallow trench, deep trench, retrograde wells,connecting implants, sub-collectors, heavily-doped buriedlayers, and buried grids - from single- to triple-wellCMOS; * practical latchup design methods, automated and bench-levellatchup testing methods and techniques, latchup theory of logarithmresistance space, generalized alpha (a) space, beta (b)space, new latchup design methods- connecting the theoreticalto the practical analysis, and; * examples of latchup computer aided design (CAD)methodologies, from design rule checking (DRC) andlogical-to-physical design, to new latchup CAD methodologiesthat address latchup for internal and external latchup on a localas well as global design level. Latchup acts as a companion text to the author'sseries of books on ESD (electrostatic discharge) protection,serving as an invaluable reference for the professionalsemiconductor chip and system-level ESD engineer. Semiconductordevice, process and circuit designers, and quality, reliability andfailure analysis engineers will find it informative on the issuesthat confront modern CMOS technology. Practitioners in theautomotive and aerospace industries will also find it useful. Inaddition, its academic treatment will appeal to both senior andgraduate students with interests in semiconductor process, devicephysics, computer aided design and design integration. eBook Steven H. Voldman PDF, John Wiley & Sons, Inc., 02.08.2008, John Wiley & Sons, Inc., 2008<

ISBN: 9780470516164

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, a… More...

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and;examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.; PDF; Scientific, Technical and Medical > Electronics & communications engineering, Wiley<

ISBN: 9780470516164

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, a… More...

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and;examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.; PDF; Scientific, Technical and Medical > Electronics & communications engineering, Wiley<

2008, ISBN: 9780470516164

Interest in latchup is being renewed with the evolution ofcomplimentary metal-oxide semiconductor (CMOS) technology,metal-oxide-semiconductor field-effect transistor (MOSFET) scaling,and … More...

Interest in latchup is being renewed with the evolution ofcomplimentary metal-oxide semiconductor (CMOS) technology,metal-oxide-semiconductor field-effect transistor (MOSFET) scaling,and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, withinsight into the physics, technology and circuit issues involved,are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology andtheir sensitivity to present day latchup phenomena, from basicover-voltage and over-current conditions, single event latchup(SEL) and cable discharge events (CDE), to latchup dominophenomena. It contains chapters focusing on bipolar physics,latchup theory, latchup and guard ring characterization structures,characterization testing, product level test systems, product leveltesting and experimental results. Discussions on state-of-the-artsemiconductor processes, design layout, and circuit level andsystem level latchup solutions are also included, as well as: * latchup semiconductor process solutions for both CMOS toBiCMOS, such as shallow trench, deep trench, retrograde wells,connecting implants, sub-collectors, heavily-doped buriedlayers, and buried grids - from single- to triple-wellCMOS; * practical latchup design methods, automated and bench-levellatchup testing methods and techniques, latchup theory of logarithmresistance space, generalized alpha (a) space, beta (b)space, new latchup design methods- connecting the theoreticalto the practical analysis, and; * examples of latchup computer aided design (CAD)methodologies, from design rule checking (DRC) andlogical-to-physical design, to new latchup CAD methodologiesthat address latchup for internal and external latchup on a localas well as global design level. Latchup acts as a companion text to the author'sseries of books on ESD (electrostatic discharge) protection,serving as an invaluable reference for the professionalsemiconductor chip and system-level ESD engineer. Semiconductordevice, process and circuit designers, and quality, reliability andfailure analysis engineers will find it informative on the issuesthat confront modern CMOS technology. Practitioners in theautomotive and aerospace industries will also find it useful. Inaddition, its academic treatment will appeal to both senior andgraduate students with interests in semiconductor process, devicephysics, computer aided design and design integration. eBook Steven H. Voldman PDF, John Wiley & Sons Inc, 02.08.2008, John Wiley & Sons Inc, 2008<