2010, ISBN: 9783639295924

Autor : Kumar, Jiwesh. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the seq… More...

Autor : Kumar, Jiwesh. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. .contentData { line-height: 14px; margin: 2px; padding: 2px; } .contentData table.mainTable { font-family:Arial, sans-serif, Verdana; font-size:13px; } .contentData td { padding-right:10px; line-height: 16px; } .contentData td.header { width: 150px; font-weight: bold; } .contentData ul { padding-left: 40px; } .contentData h2 { font-family:Arial, sans-serif, Verdana; font-size: 24px; margin: 18px 0 18px 0; font-weight: 700; } .contentData h3 { font-family:Arial, sans-serif, Verdana; font-size: 18px; margin: 18px 0 18px 0; font-weight: 700; } .contentData p { font-family:Arial, sans-serif, Verdana; font-size: 12px; margin: 12px 0 12px 0; } .contentData li { font-family:Arial, sans-serif, Verdana!important; font-size: 12px; } Allgemein Titel: FPGA Implementation of MPEG-2 Video decoder - FPGA Implementation of base layer MPEG-2 Video decoder Genre: Herstellungs- & Verfahrenstechnik Medientyp: Taschenbuch Beschreibung The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program" board. Weitere Informationen Sprache: Englisch Seitenanzahl: 72 Verlag: VDM Verlag Dr. Müller Verpackungsabmessungen: 0.22m x 0.15m x 0.004m Mitwirkende Autor: Kumar, Jiwesh Autor: Pandey, Pranjal , Neu, Festpreisangebot, [LT: FixedPrice], EAN: 9783639295924, Format: Taschenbuch, Anzahl der Seiten: 72 Seiten, Publikationsname: Fpga Implementation of Mpeg-2 Video Decoder, Sprache: Englisch, Vdm Verlag, 2010<

ISBN: 9783639295924

Paperback, [PU: VDM Verlag], The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related int… More...

Paperback, [PU: VDM Verlag], The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 "university program" board., Engineering: General<

2010, ISBN: 9783639295924

VDM Verlag Dr. Müller, Taschenbuch, 72 Seiten, Publiziert: 2010-09-17T00:00:01Z, Produktgruppe: Buch, 0.26 kg, Maschinenbau, Ingenieurwissenschaften, Fachbücher, Kategorien, Bücher, Ingen… More...

VDM Verlag Dr. Müller, Taschenbuch, 72 Seiten, Publiziert: 2010-09-17T00:00:01Z, Produktgruppe: Buch, 0.26 kg, Maschinenbau, Ingenieurwissenschaften, Fachbücher, Kategorien, Bücher, Ingenieurwissenschaft & Technik, Naturwissenschaften & Technik, VDM Verlag Dr. Müller, 2010<

2010, ISBN: 9783639295924

VDM Verlag Dr. Müller, Taschenbuch, 72 Seiten, Publiziert: 2010-09-17T00:00:01Z, Produktgruppe: Buch, 0.26 kg, Maschinenbau, Ingenieurwissenschaften, Fachbücher, Kategorien, Bücher, Ingen… More...

VDM Verlag Dr. Müller, Taschenbuch, 72 Seiten, Publiziert: 2010-09-17T00:00:01Z, Produktgruppe: Buch, 0.26 kg, Maschinenbau, Ingenieurwissenschaften, Fachbücher, Kategorien, Bücher, Ingenieurwissenschaft & Technik, Naturwissenschaften & Technik, VDM Verlag Dr. Müller, 2010<

2010, ISBN: 9783639295924

Paperback, Neubuch, BRAND NEW BOOK! Shipped within 24-48 hours. Normal delivery time is 5-12 days. Please note some orders may be shipped from UK with same delivery timeframe, ***NO EXPED… More...

Paperback, Neubuch, BRAND NEW BOOK! Shipped within 24-48 hours. Normal delivery time is 5-12 days. Please note some orders may be shipped from UK with same delivery timeframe, ***NO EXPEDITED ORDERS***, [PU: VDM Verlag Dr. M�ller]<